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Varadharajan : (408)-219-9400

About the Design Team

Varadharajan.S (RAJ)                              
Designer with 20 years of commendable experience in high speed, complex PCB designs and projects
Very successful with completion of projects on time and with constraints. 
  • High Speed PCB Design Experience;
    • Worked up to 28 Layer PCB and Gigabit speeds
    • Good understanding of the impedance control mechanisms in PCB 
    • Experienced in high Clock routing, Back plane routing 
  • IPC certified inter connect designer (C.I.D)
  • 12+ years of experience using the Cadence Allegro PCB Design Tool
  • Worked in Mentor Graphics PCB design Tool
  • Experience in Spectra Auto router
  • Worked in the Platforms like
    • DEC PDP II with EIE paragon software
    • HP, Sun Work  & Pentium Work Stations running Allegro &  Mentor Graphics Tools.
  • Worked with Design Engineers on the SI (Signal Integrity issues) with tools like XTK
  • Familiar with Auto CAD and used to work with DXF files to import the Board mechanicals to Allegro.
  • Familiar with output requirement for PRO-E Mechanical Tool from Allegro
  • Very knowledgeable on all industry standard DFM & DFT requirements 
  • Hands on Experience with all post processing work for FAB out.
  • Worked with PCB Fabrication house in the US and Asia and have a complete understanding of their input requirements for PCB fabrication.
  • Served  in the following originations WIPRO ( INDIA), FORCE COMPUTERS (INDIA),NOKIA(USA)

Venkata Ramanan  

Designer with 10 years Industry presence in various fields and multitude of experience
  • Skills include mastering the tools like
    • Cadence Allegro, SpecctraQuest, Specctra
    • Mentor HyperLynx, EPD/Viewlogic
  • Capabilities include
    • Pre-Layout Simulation/Evaluation Of Logical Families
    • Control Impedance Estimation Stack-Up Prediction
    • Pre-Layout Reflection, Crosstalk, Coupling Simulation
    • Differential Impedance Estimation And Planning
    • Decoupling Selection And Allotment
    • Constraint Management, Constraint Assigning
    • Placement Evaluation, Decoupling Distribution
    • Constraint Driven Routing
    • Post-Layout Topology Verification
    • Post-Layout Crosstalk, Coupling, Reflection, SSN Simulation
    • Post-Layout Intelligent Net Length/Topology Report Generation
    • ODB++ Data Generation and pre/post FAB support
    • HP, Sun Work  & Pentium Work Stations running Allegro &  Mentor Graphics Tools.
  • Viewlogic custom library creation, BOM/AVL maintenance

 

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